LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 472

• Manufacturer Part Number: LM3S3768
• Description: Lm3s3768 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Inter-Integrated Circuit (I
16.2.3
16.2.3.1 I
16.2.3.2 I
472
Interrupts
The I
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There is a separate interrupt signal for the I
can generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt
controller.
The I
receive), or when an error occurs during a transaction. To enable the I
must write a '1' to the I
is met, software must check the ERROR bit in the I
verify that an error didn't occur during the last transaction. An error condition is asserted if the last
transaction wasn't acknowledge by the slave or if the master was forced to give up ownership of
the bus due to a lost arbitration round with another master. If an error is not detected, the application
can proceed with the transfer. The interrupt is cleared by writing a '1' to the I
Clear (I2CMICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I
The slave module generates interrupts as it receives data and transmit requests from an I
The slave module also generates interrupts when a start and stop condition is detected. To enable
an I
register. Software determines whether the module should write (transmit) or read (receive) data
from the I
Control/Status (I2CSCSR) register. If the slave module is in receive mode and the first byte of a
transfer is received, the FBR bit is set along with the RREQ bit. The interrupt is cleared by writing a
'1' to the I
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I
System Clock
2
2
C Master Interrupts
C Slave Interrupts
Master transaction completed
Master transaction error
Slave transaction received
Slave transaction requested
Stop condition on bus detected
Start condition on bus detected
50Mhz
2
2
2
C slave interrupt, write a '1' to the appropriate bit in the I
2
2
C Master Raw Interrupt Status (I2CMRIS) register.
C Slave Raw Interrupt Status (I2CSRIS) register.
C can generate interrupts when the following conditions are observed:
C master module generates an interrupt when a transaction completes (either transmit or
2
2
C Slave Data (I2CSDR) register, by checking the RREQ and TREQ bits of the I
C Slave Interrupt Clear (I2CSICR) register.
2
C) Interface
Timer Period
0x18
2
C Master Interrupt Mask (I2CMIMR) register. When an interrupt condition
Standard Mode
100 Kbps
Preliminary
Timer Period
2
0x06
C master and I
2
C Master Control/Status (I2CMCS) register to
Fast Mode
357 Kbps
2
C slave modules. While both modules
2
C Slave Interrupt Mask (I2CSIMR)
2
C master interrupt, software
2
C Master Interrupt
June 02, 2008
2
2
C master.
C Slave