LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 281

• Manufacturer Part Number: LM3S3768
• Description: Lm3s3768 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
GPIO Commit (GPIOCR)
GPIO Port A (legacy) base: 0x4000.4000
GPIO Port A (high-speed) base: 0x4005.8000
GPIO Port B (legacy) base: 0x4000.5000
GPIO Port B (high-speed) base: 0x4005.9000
GPIO Port C (legacy) base: 0x4000.6000
GPIO Port C (high-speed) base: 0x4005.A000
GPIO Port D (legacy) base: 0x4000.7000
GPIO Port D (high-speed) base: 0x4005.B000
GPIO Port E (legacy) base: 0x4002.4000
GPIO Port E (high-speed) base: 0x4005.C000
GPIO Port F (legacy) base: 0x4002.5000
GPIO Port F (high-speed) base: 0x4005.D000
GPIO Port G (legacy) base: 0x4002.6000
GPIO Port G (high-speed) base: 0x4005.E000
GPIO Port H (legacy) base: 0x4002.7000
GPIO Port H (high-speed) base: 0x4005.F000
Offset 0x524
Type -, reset -
June 02, 2008
Bit/Field
31:8
RO
RO
31
15
0
0
RO
RO
Register 20: GPIO Commit (GPIOCR), offset 0x524
The GPIOCR register is the commit register. The value of the GPIOCR register determines which
bits of the GPIOAFSEL, GPIOPUR, and GPIODEN registers are committed when a write to these
registers is performed. If a bit in the GPIOCR register is zero, the data being written to the
corresponding bit in the GPIOAFSEL, GPIOPUR, or GPIODEN registers cannot be committed and
retains its previous value. If a bit in the GPIOCR register is set, the data being written to the
corresponding bit of the GPIOAFSEL, GPIOPUR, or GPIODEN registers is committed to the register
and reflects the new value.
The contents of the GPIOCR register can only be modified if the GPIOLOCK register is unlocked.
Writes to the GPIOCR register are ignored if the GPIOLOCK register is locked.
Important:
30
14
0
0
RO
RO
29
13
reserved
0
0
Name
This register is designed to prevent accidental programming of the registers that control
connectivity to the NMI and JTAG/SWD debug hardware. By initializing the bits of the
GPIOCR register to 0 for PB7 and PC[3:0], the NMI and JTAG/SWD debug port can
only be converted to GPIOs through a deliberate set of writes to the GPIOLOCK,
GPIOCR, and the corresponding registers.
Because this protection is currently only implemented on the NMI and JTAG/SWD pins
on PB7 and PC[3:0], all of the other bits in the GPIOCR registers cannot be written
with 0x0. These bits are hardwired to 0x1, ensuring that it is always possible to commit
new values to the GPIOAFSEL, GPIOPUR, or GPIODEN register bits of these other
pins.
RO
RO
28
12
0
0
reserved
RO
RO
27
11
0
0
Type
RO
RO
RO
26
10
0
0
RO
RO
Reset
25
0x00
0
9
0
Preliminary
RO
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RO
23
0
7
-
-
RO
22
0
6
-
-
RO
21
0
5
-
-
RO
20
0
4
-
-
CR
RO
19
0
3
-
-
LM3S3768 Microcontroller
RO
18
0
2
-
-
RO
17
0
1
-
-
RO
16
0
0
-
-
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