LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 44

• Manufacturer Part Number: LM3S3768
• Description: Lm3s3768 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

ARM Cortex-M3 Processor Core
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
44
Serial Wire and JTAG Debug
Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant
Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, “Debug Port,” of the
ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris
The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the
CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP.
Embedded Trace Macrocell (ETM)
ETM was not implemented in the Stellaris
Cortex™-M3 Technical Reference Manual can be ignored.
Trace Port Interface Unit (TPIU)
The TPIU acts as a bridge between the Cortex-M3 trace data from the ITM, and an off-chip Trace
Port Analyzer. The Stellaris
This is similar to the non-ETM version described in the ARM® Cortex™-M3 Technical Reference
Manual, however, SWJ-DP only provides SWV output for the TPIU.
Figure 2-2. TPIU Block Diagram
ROM Table
The default ROM table was implemented as described in the ARM® Cortex™-M3 Technical
Reference Manual.
Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) is included on the LM3S3768 controller and supports the standard
ARMv7 Protected Memory System Architecture (PMSA) model. The MPU provides full support for
protection regions, overlapping protection regions, access permissions, and exporting memory
attributes to the system.
Debug
Slave
Slave
APB
ATB
Port
Port
Interface
Interface
APB
ATB
®
devices have implemented TPIU as shown in Figure 2-2 on page 44.
Asynchronous FIFO
Preliminary
®
devices. This means Chapters 15 and 16 of the ARM®
(serializer)
Trace Out
®
Serial Wire
Trace Port
devices.
(SWO)
June 02, 2008