LM3S3768 Luminary Micro, Inc, LM3S3768 Datasheet - Page 652

• Manufacturer Part Number: LM3S3768
• Description: Lm3s3768 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Reset
Type
Type
Pulse Width Modulator (PWM)
PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL)
Base 0x4002.8000
Offset 0x070
Type R/W, reset 0x0000.0000
652
Bit/Field
31:12
11:0
RO
RO
31
15
0
0
RO
RO
Register 59: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset
0x070
Register 60: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset
0x0B0
Register 61: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset
0x0F0
Register 62: PWM3 Dead-Band Falling-Edge-Delay (PWM3DBFALL), offset
0x130
The PWM0DBFALL register contains the number of clock ticks to delay the falling edge of the
PWM0A signal when generating the PWM1 signal. If the dead-band generator is disabled, this register
is ignored. If the value of this register is larger than the width of a Low pulse on the input PWM
signal, the falling-edge delay consumes the entire Low time of the signal, resulting in no Low time
on the output. Care must be taken to ensure that the input Low time always exceeds the falling-edge
delay. In a similar manner, PWM3 is generated from PWM1A with its falling edge delayed, PWM5 is
produced from PWM2A with its falling edge delayed, and PWM7 is produced from PWM3A with its falling
edge delayed.
If the Dead-Band Falling-Edge-Delay mode is immediate (based on the DBFallUp field encoding
in the PWMnCTL register), this 16-bit DBFallUp value is used the next time the counter reaches
zero. If the update mode is synchronous, it is used the next time the counter reaches zero after a
synchronous update has been requested through the PWM Master Control (PWMCTL) register
(see page 615). If this register is rewritten before the actual update occurs, the previous value is
never used and is lost.
30
14
0
0
reserved
RO
RO
29
13
FallDelay
reserved
0
0
Name
RO
RO
28
12
0
0
R/W
RO
27
11
0
0
Type
R/W
RO
R/W
RO
26
10
0
0
R/W
RO
Reset
25
0x00
0x00
0
9
0
Preliminary
R/W
RO
24
0
8
0
reserved
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Dead-Band Fall Delay
The number of clock ticks to delay the falling edge.
R/W
RO
23
0
7
0
R/W
RO
22
0
6
0
FallDelay
R/W
RO
21
0
5
0
R/W
RO
20
0
4
0
R/W
RO
19
0
3
0
R/W
RO
18
0
2
0
R/W
RO
17
0
1
0
June 02, 2008
R/W
RO
16
0
0
0