MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 203

• Manufacturer Part Number: MC9S12XEQ512CAL
• Description: MCU 16BIT 512K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEQ512CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 32KB
• Cpu Speed: 50MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.3.2.5
Read: Anytime. In emulation modes read operations will return the data from the external bus. In all other
modes the data are read from this register.
Write: Refer to each bit description. In emulation modes write operations will also be directed to the
external bus.
Freescale Semiconductor
Address: 0x0013 PRR
TGMRAMON
PGMIFRON
EEEIFRON
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
RAMHM
Reset
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
Field
7
5
4
3
W
R
TGMRAMON
EEE Tag RAM and FTM SCRATCH RAM visible in the memory map
Write: Anytime
This bit is used to made the EEE Tag RAM nd FTM SCRATCH RAM visible in the global memory map.
0 Not visible in the memory map.
1 Visible in the memory map.
EEE IFR visible in the memory map
Write: Anytime
This bit is used to made the IFR sector of EEE DATA FLASH visible in the global memory map.
0 Not visible in the memory map.
1 Visible in the memory map.
Program IFR visible in the memory map
Write: Anytime
This bit is used to made the IFR sector of the Program Flash visible in the global memory map.
0 Not visible in the memory map.
1 Visible in the memory map.
RAM only in higher Half of the memory map
Write: Once in normal and emulation modes and anytime in special modes
0 Accesses to $4000–$7FFF will be mapped to $14_4000-$14_7FFF in the global memory space (external
1 Accesses to $4000–$7FFF will be mapped to $0F_C000-$0F_FFFF in the global memory space (RAM area).
MMC Control Register (MMCCTL1)
0
7
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
access).
= Unimplemented or Reserved
0
0
6
Figure 3-10. MMC Control Register (MMCCTL1)
MC9S12XE-Family Reference Manual Rev. 1.23
Table 3-11. MMCCTL1 Field Descriptions
EEEIFRON
5
0
;many cases assemblers are “direct page aware” and can
;automatically select direct mode.
PGMIFRON
CAUTION
0
4
Description
RAMHM
0
3
Chapter 3 Memory Mapping Control (S12XMMCV4)
EROMCTL
EROMON
2
ROMHM
0
1
ROMCTL
ROMON
0
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