MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 221

• Manufacturer Part Number: MC9S12XEQ512CAL
• Description: MCU 16BIT 512K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEQ512CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 32KB
• Cpu Speed: 50MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3.4.3
CPU and XGATE accesses are watched in the memory protection unit (See MPU Block Guide). In case of
access violation, the suspect master is acknowledged with an indication of an error; the victim target will
not be accessed.
Other violations MPU is not handling are listed below.
3.4.3.1
A possible access error is flagged by the MMC and signalled to XGATE under the following conditions:
For further details refer to the XGATE Block Guide.
3.4.4
The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM and
XGATE) with the rest of the system (master buses). In addition the MMC handles all CPU read data bus
swapping operations. All internal and external resources are connected to specific target buses (see
Figure 3-23
1. Doted blocks and lines are optional. Please refer to the Device User Guide for their availlibilities.
Freescale Semiconductor
Because of an order from the United States International Trade Commission, BGA-packaged product lines and partnumbers
indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010
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•
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XGATE performs misaligned word (in case of load-store or opcode or vector fetch accesses).
XGATE accesses the register space (in case of opcode or vector fetch).
XGATE performs a write to Flash in any modes (in case of load-store access).
XGATE performs an access to a secured Flash in expanded modes (in case of load-store or opcode
or vector fetch accesses).
1
Chip Access Restrictions
Chip Bus Control
).
Illegal XGATE Accesses
MC9S12XE-Family Reference Manual Rev. 1.23
Chapter 3 Memory Mapping Control (S12XMMCV4)
221