MC9S12XEQ512CAL Freescale Semiconductor, MC9S12XEQ512CAL Datasheet - Page 955

• Manufacturer Part Number: MC9S12XEQ512CAL
• Description: MCU 16BIT 512K FLASH 112-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XEQ512CAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 112-LQFP
• No. Of I/o's: 91
• Eeprom Memory Size: 4KB
• Ram Memory Size: 32KB
• Cpu Speed: 50MHz
• No. Of Timers: 3
• No. Of Pwm Channels: 8
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: S12XE
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 25
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: KIT33812ECUEVME, EVB9S12XEP100, DEMO9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 26
384 KByte Flash Module (S12XFTM384K2V1)
26.1
The FTM384K2 module implements the following:
Freescale Semiconductor
Revision
Number
V01.10
V01.11
V01.12
•
•
384 Kbytes of P-Flash (Program Flash) memory, consisting of 2 physical Flash blocks, intended
primarily for nonvolatile code storage
32 Kbytes of D-Flash (Data Flash) memory, consisting of 1 physical Flash block, that can be used
as nonvolatile storage to support the built-in hardware scheme for emulated EEPROM, as basic
Flash memory primarily intended for nonvolatile data storage, or as a combination of both
Introduction
29 Nov 2007
19 Dec 2007
25 Sep 2009
Revision
Date
26.3.2.1/26-967
26.4.2.4/26-994
26.4.2.7/26-997
26.3.2.1/26-967
26.4.1.2/26-986
26.4.2/26-991
26.4.2/26-991
26.3.1/26-960
26.3.2/26-965
26.4.2.12/26-
26.4.2.12/26-
26.4.2.12/26-
26.4.2.20/26-
26.6/26-1016
26.1/26-955
Sections
Affected
1001
1001
1001
1010
MC9S12XE-Family Reference Manual , Rev. 1.23
Table 26-1. Revision History
- Cleanup
- Updated Command Error Handling tables based on parent-child relationship
with FTM512K3
- Corrected Error Handling table for Full Partition D-Flash, Partition D-Flash,
and EEPROM Emulation Query commands
- Corrected P-Flash IFR Accessibility table
- Clarify single bit fault correction for P-Flash phrase
- Expand FDIV vs OSCCLK Frequency table
- Add statement concerning code runaway when executing Read Once
command from Flash block containing associated fields
- Add statement concerning code runaway when executing Program Once
command from Flash block containing associated fields
- Add statement concerning code runaway when executing Verify Backdoor
Access Key command from Flash block containing associated fields
- Relate Key 0 to associated Backdoor Comparison Key address
- Change “power down reset” to “reset”
- Add ACCERR condition for Disable EEPROM Emulation command
The following changes were made to clarify module behavior related to Flash
register access during reset sequence and while Flash commands are active:
- Add caution concerning register writes while command is active
- Writes to FCLKDIV are allowed during reset sequence while CCIF is clear
- Add caution concerning register writes while command is active
- Writes to FCCOBIX, FCCOBHI, FCCOBLO registers are ignored during
reset sequence
Description of Changes
955