D13008VXI25V Renesas Electronics America, D13008VXI25V Datasheet - Page 165

• Manufacturer Part Number: D13008VXI25V
• Description: MCU 3V 0K I-TEMP PB-FREE 100-TQF
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13008VXI25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 6.3
ABWCR ASTCR WCRH/WCRL
ABWn
0
1
Note: n = 0 to 7
6.3.3
As its memory interface, the H8/3008 has only a basic bus interface that allows direct connection
of ROM, SRAM, and so on. It is not possible to select a DRAM interface that allows direct
connection of DRAM, or a burst ROM interface that allows direct connection of burst ROM.
6.3.4
For each of areas 0 to 7, the H8/3008 can output a chip select signal (CS
when the corresponding area is selected in expanded mode. Figure 6.4 shows the output timing of
a CSn signal.
Output of CS
(DDR) of the corresponding port.
In the expanded modes with on-chip ROM disabled, a reset leaves pin CS
pins CS
bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins CS
CS
be set to 1. For details, see section 7, I/O Ports.
3
in the input state. To output chip select signals CS
1
to CS
ASTn
0
1
0
1
Memory Interfaces
Chip Select Signals
Bus Specifications for Each Area (Basic Bus Interface)
0
3
to CS
in the input state. To output chip select signals CS
Wn1
⎯
0
1
⎯
0
1
3
: Output of CS
Wn0
⎯
0
1
0
1
⎯
0
1
0
1
0
to CS
Bus Specifications (Basic Bus Interface)
Bus Width
16
8
3
is enabled or disabled in the data direction register
Access States
2
3
2
3
0
to CS
Rev.4.00 Aug. 20, 2007 Page 119 of 638
3
, the corresponding DDR bits must
1
to CS
0
3
to CS
, the corresponding DDR
0
in the output state and
Program Wait States
0
0
1
2
3
0
0
1
2
3
7
) that goes low
REJ09B0395-0400
6. Bus Controller
0
to