D13008VXI25V Renesas Electronics America, D13008VXI25V Datasheet - Page 561
D13008VXI25V
Manufacturer Part Number
D13008VXI25V
Description
MCU 3V 0K I-TEMP PB-FREE 100-TQF
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of D13008VXI25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
- Current page: 561 of 688
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A.3
The tables in this section can be used to calculate the number of states required for instruction
execution by the H8/300H CPU. Table A.4 indicates the number of instruction fetch, data
read/write, and other cycles occurring in each instruction. Table A.3 indicates the number of states
required per cycle according to the bus size. The number of states required for execution of an
instruction can be calculated from these two tables as follows:
Number of states = I × S
Examples of Calculation of Number of States Required for Execution
Examples: Advanced mode, stack located in external address space, on-chip supporting modules
accessed with 8-bit bus width, external devices accessed in three states with one wait state and
16-bit bus width.
BSET #0, @FFFFC7:8
JSR @@30
From table A.4, I = L = 2 and J = K = M = N = 0
From table A.3, S
Number of states = 2 × 4 + 2 × 3 = 14
From table A.4, I = J = K = 2 and L = M = N = 0
From table A.3, S
Number of states = 2 × 4 + 2 × 4 + 2 × 4 = 24
Number of States Required for Execution
I
+ J × S
I
I
= 4 and S
= S
J
= S
J
+ K × S
K
L
= 4
= 3
K
+ L × S
L
+ M × S
Rev.4.00 Aug. 20, 2007 Page 515 of 638
M
+ N × S
N
Appendix A Instruction Set
REJ09B0395-0400
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