D13008VXI25V Renesas Electronics America, D13008VXI25V Datasheet - Page 21

• Manufacturer Part Number: D13008VXI25V
• Description: MCU 3V 0K I-TEMP PB-FREE 100-TQF
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13008VXI25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

5.2
5.3
5.4
5.5
Section 6 Bus Controller
6.1
6.2
6.3
5.1.2
5.1.3
5.1.4
Register Descriptions ........................................................................................................ 78
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
Interrupt Sources ............................................................................................................... 87
5.3.1
5.3.2
5.3.3
Interrupt Operation............................................................................................................ 92
5.4.1
5.4.2
5.4.3
Usage Notes ...................................................................................................................... 99
5.5.1
5.5.2
5.5.3
Overview........................................................................................................................... 101
6.1.1
6.1.2
6.1.3
6.1.4
Register Descriptions ........................................................................................................ 104
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
Operation........................................................................................................................... 116
6.3.1
6.3.2
6.3.3
Block Diagram ..................................................................................................... 76
Pin Configuration................................................................................................. 77
Register Configuration......................................................................................... 77
System Control Register (SYSCR) ...................................................................... 78
Interrupt Priority Registers A and B (IPRA, IPRB) ............................................. 79
IRQ Status Register (ISR).................................................................................... 84
IRQ Enable Register (IER) .................................................................................. 85
IRQ Sense Control Register (ISCR) .................................................................... 86
External Interrupts ............................................................................................... 87
Internal Interrupts................................................................................................. 88
Interrupt Exception Handling Vector Table......................................................... 88
Interrupt Handling Process................................................................................... 92
Interrupt Exception Handling Sequence .............................................................. 97
Interrupt Response Time...................................................................................... 98
Contention between Interrupt and Interrupt-Disabling Instruction ...................... 99
Instructions that Inhibit Interrupts........................................................................ 100
Interrupts during EEPMOV Instruction Execution .............................................. 100
Features................................................................................................................ 101
Block Diagram ..................................................................................................... 102
Pin Configuration................................................................................................. 103
Register Configuration......................................................................................... 104
Bus Width Control Register (ABWCR)............................................................... 104
Access State Control Register (ASTCR) ............................................................. 105
Wait Control Registers H and L (WCRH, WCRL).............................................. 106
Bus Release Control Register (BRCR) ................................................................ 110
Bus Control Register (BCR) ................................................................................ 111
Chip Select Control Register (CSCR).................................................................. 114
Address Control Register (ADRCR).................................................................... 115
Area Division ....................................................................................................... 116
Bus Specifications................................................................................................ 118
Memory Interfaces ............................................................................................... 119
.................................................................................................... 101
Rev.4.00 Aug. 20, 2007, Page xix of xliv
REJ09B0395-0400