D13008VXI25V Renesas Electronics America, D13008VXI25V Datasheet - Page 37

• Manufacturer Part Number: D13008VXI25V
• Description: MCU 3V 0K I-TEMP PB-FREE 100-TQF
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13008VXI25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 14.4
Figure 14.5
Figure 14.6
Figure 14.7
Figure 14.8
Figure 14.9
Figure 14.10
Figure 14.11
Section 15 D/A Converter
Figure 15.1
Figure 15.2
Section 16 RAM
Figure 16.1
Section 17 Clock Pulse Generator
Figure 17.1
Figure 17.2
Figure 17.3
Figure 17.4
Figure 17.5
Figure 17.6
Figure 17.7
Section 18 Power-Down State
Figure 18.1
Figure 18.2
Figure 18.3
Section 19 Electrical Characteristics
Figure 19.1
Figure 19.2
Figure 19.3
Figure 19.4
Figure 19.5
Figure 19.6
Figure 19.7
Figure 19.8
Example of A/D Converter Operation
(Scan Mode, Channels AN
A/D Conversion Timing ..................................................................................... 426
External Trigger Input Timing ........................................................................... 427
Example of Analog Input Protection Circuit ...................................................... 429
Analog Input Pin Equivalent Circuit .................................................................. 429
A/D Converter Accuracy Definitions (1) ........................................................... 431
A/D Converter Accuracy Definitions (2) ........................................................... 432
Analog Input Circuit (Example) ......................................................................... 433
D/A Converter Block Diagram........................................................................... 436
Example of D/A Converter Operation................................................................ 441
RAM Block Diagram ......................................................................................... 444
Block Diagram of Clock Pulse Generator .......................................................... 448
Connection of Crystal Resonator (Example) ...................................................... 449
Crystal Resonator Equivalent Circuit ................................................................. 450
Oscillator Circuit Block Board Design Precautions ........................................... 451
External Clock Input (Examples) ....................................................................... 451
External Clock Input Timing.............................................................................. 453
External Clock Output Settling Delay Timing ................................................... 453
NMI Timing for Software Standby Mode (Example) ........................................ 467
Hardware Standby Mode Timing ....................................................................... 469
Starting and Stopping of System Clock Output.................................................. 470
Darlington Pair Drive Circuit (Example) ........................................................... 478
Output Load Circuit............................................................................................ 484
Oscillator Settling Timing .................................................................................. 488
Reset Input Timing ............................................................................................. 489
Reset Output Timing .......................................................................................... 489
Interrupt Input Timing........................................................................................ 490
Basic Bus Cycle: Two-State Access................................................................... 492
Basic Bus Cycle: Three-State Access................................................................. 493
0
to AN
2
Selected) .................................................... 424
Rev.4.00 Aug. 20, 2007, Page xxxv of xliv
REJ09B0395-0400