D13008VXI25V Renesas Electronics America, D13008VXI25V Datasheet - Page 336

MCU 3V 0K I-TEMP PB-FREE 100-TQF

D13008VXI25V

Manufacturer Part Number
D13008VXI25V
Description
MCU 3V 0K I-TEMP PB-FREE 100-TQF
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of D13008VXI25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
10. Programmable Timing Pattern Controller (TPC)
Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered
by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFFA5
and the address of the lower 4 bits (group 0) is H'FFFA7. Bits 3 to 0 of address H'FFFA5 and bits
7 to 4 of address H'FFFA7 are reserved bits that cannot be modified and always read 1.
Address H'FFFA5
Address H'FFFA7
Rev.4.00 Aug. 20, 2007 Page 290 of 638
REJ09B0395-0400
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
NDR7
R/W
7
1
7
0
Next data 7 to 4
These bits store the next output
data for TPC output group 1
NDR6
Reserved bits
R/W
6
1
6
0
NDR5
R/W
5
1
5
0
NDR4
R/W
4
1
4
0
NDR3
R/W
3
0
3
1
Next data 3 to 0
These bits store the next output
data for TPC output group 0
NDR2
R/W
Reserved bits
2
0
2
1
NDR1
R/W
1
0
1
1
NDR0
R/W
0
0
0
1

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