D13008VXI25V Renesas Electronics America, D13008VXI25V Datasheet - Page 312

• Manufacturer Part Number: D13008VXI25V
• Description: MCU 3V 0K I-TEMP PB-FREE 100-TQF
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13008VXI25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

9. 8-Bit Timers
16-Bit Count Mode
• Channels 0 and 1:
• Channels 2 and 3:
Rev.4.00 Aug. 20, 2007 Page 266 of 638
REJ09B0395-0400
When bits CKS2 to CKS0 are set to (100) in 8TCR0, the timer functions as a single 16-bit
timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
⎯ Setting when Compare Match Occurs
⎯ Setting when Input Capture Occurs
⎯ Counter Clear Specification
⎯ OVF Flag Operation
When bits CKS2 to CKS0 are set to (100) in 8TCR2, the timer functions as a single 16-bit
timer with channel 2 occupying the upper 8 bits and channel 3 occupying the lower 8 bits.
⎯ Setting when Compare Match Occurs
• The CMFA or CMFB flag is set to 1 in 8TCSR0 when a 16-bit compare match occurs.
• The CMFA or CMFB flag is set to 1 in 8TCSR1 when a lower 8-bit compare match
• TMO
• TMIO
• The CMFB flag is set to 1 in 8TCSR0 and 8TCSR1 when the ICE bit is 1 in TCSR1
• TMIO
• If counter clear on compare match or input capture has been selected by the CCLR1
• The settings of the CCLR1 and CCLR0 bits in 8TCR1 are ignored. The lower 8 bits
• The OVF flag is set to 1 in 8TCSR0 when the 16-bit counter (8TCNT0 and 8TCNT1)
• The OVF flag is set to 1 in 8TCSR1 when the 8-bit counter (8TCNT1) overflows (from
• The CMFA or CMFB flag is set to 1 in 8TCSR2 when a 16-bit compare match occurs.
• The CMFA or CMFB flag is set to 1 in 8TCSR3 when a lower 8-bit compare match
• TMO
occurs.
accordance with the 16-bit compare match conditions.
accordance with the lower 8-bit compare match conditions.
and input capture occurs.
in 8TCSR0.
and CCLR0 bits in 8TCR0, the 16-bit counter (both 8TCNT0 and 8TCNT1) is cleared.
cannot be cleared independently.
overflows (from H'FFFF to H'0000).
H'FF to H'00).
occurs.
accordance with the 16-bit compare match conditions.
0
2
1
1
pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR0 is in
pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR2 is in
pin output control by bits OIS3, OIS2, OS1, and OS0 in 8TCSR1 is in
pin input capture input signal edge detection is selected by bits OIS3 and OIS2