D13008VXI25V Renesas Electronics America, D13008VXI25V Datasheet - Page 48

• Manufacturer Part Number: D13008VXI25V
• Description: MCU 3V 0K I-TEMP PB-FREE 100-TQF
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13008VXI25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

1. Overview
Table 1.1
Feature
CPU
Memory
Interrupt
controller
Bus controller
Rev.4.00 Aug. 20, 2007 Page 2 of 638
REJ09B0395-0400
Features
Description
Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
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High-speed operation
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16-Mbyte address space
Instruction features
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Bit manipulation instructions with register-indirect specification of bit positions
H8/3008
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Sixteen 16-bit general registers
(also usable as sixteen 8-bit registers plus eight 16-bit registers, or as eight
32-bit registers)
Maximum clock rate: 25 MHz
Add/subtract: 80 ns
Multiply/divide: 560 ns
8/16/32-bit data transfer, arithmetic, and logic instructions
Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16 bits)
Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
Bit accumulator function
RAM: 4 kbytes
Seven external interrupt pins: NMI, IRQ
27 internal interrupts
Three selectable interrupt priority levels
Address space can be partitioned into eight areas, with independent bus
specifications in each area
Chip select output available for areas 0 to 7
8-bit access or 16-bit access selectable for each area
Two-state or three-state access selectable for each area
Selection of two wait modes
Number of program wait states selectable for each area
Bus arbitration function
Two address update modes
0
to IRQ
5