D13008VXI25V Renesas Electronics America, D13008VXI25V Datasheet - Page 170

MCU 3V 0K I-TEMP PB-FREE 100-TQF

D13008VXI25V

Manufacturer Part Number
D13008VXI25V
Description
MCU 3V 0K I-TEMP PB-FREE 100-TQF
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheets

Specifications of D13008VXI25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
6. Bus Controller
Table 6.4
Area
8-bit access
area
16-bit access
area
Notes: 1. Undetermined data means that unpredictable data is output.
6.4.4
The initial state of each area is basic bus interface, three-state access space. The initial bus width is
selected according to the operating mode.
Areas 0 to 6: In the H8/3008, the entire space of areas 0 to 6 is external space.
When area 0 to 6 external space is accessed, the CS
The size of areas 0 to 6 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 and 4.
Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In the H8/3008, the space
excluding the on-chip RAM and I/O registers is external space. The on-chip RAM is enabled when
the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to
0, the on-chip RAM is disabled and the corresponding space becomes external space .
When area 7 external space is accessed, the CS
The size of area 7 is 128 kbytes in modes 1 and 2, and 2 Mbytes in modes 3 and 4.
Rev.4.00 Aug. 20, 2007 Page 124 of 638
REJ09B0395-0400
2. Invalid means that the bus is in the input state and the input is ignored.
Memory Areas
Data Buses Used and Valid Strobes
Access
Size
Byte
Byte
Word
Read/
Write
Read
Write
Read
Write
Read
Write
Address
Even
Odd
Even
Odd
7
Valid
Strobe
RD
HWR
RD
HWR
LWR
RD
HWR,
LWR
signal can be output.
0
to CS
Upper Data Bus
(D
Valid
Valid
Invalid
Valid
Undetermined data Valid
Valid
Valid
6
pin signals respectively can be output.
15
to D
8
)
Lower Data Bus
(D
Invalid
Undetermined data
Invalid
Valid
Undetermined data
Valid
Valid
7
to D
0
)

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