D13008VXI25V Renesas Electronics America, D13008VXI25V Datasheet - Page 184

• Manufacturer Part Number: D13008VXI25V
• Description: MCU 3V 0K I-TEMP PB-FREE 100-TQF
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13008VXI25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6. Bus Controller
External Bus Master: When the BRLE bit is set to 1 in BRCR, the bus can be released to an
external bus master. The external bus master has highest priority, and requests the bus right from
the bus arbiter driving the BREQ signal low. Once the external bus master acquires the bus, it
keeps the bus until the BREQ signal goes high. While the bus is released to an external bus
master, the H8/3008 chip holds the address bus, data bus, bus control signals (AS, RD, HWR, and
LWR), and chip select signals (CSn: n = 7 to 0) in the high-impedance state, and holds the BACK
pin in the low output state.
The bus arbiter samples the BREQ pin at the rise of the system clock (φ). If BREQ is low, the bus
is released to the external bus master at the appropriate opportunity. The BREQ signal should be
held low until the BACK signal goes low.
When the BREQ pin is high in two consecutive samples, the BACK pin is driven high to end the
bus-release cycle.
Figure 6.21 shows the timing when the bus right is requested by an external bus master during a
read cycle in a two-state access area. There is a minimum interval of three states from when the
BREQ signal goes low until the bus is released.
Rev.4.00 Aug. 20, 2007 Page 138 of 638
REJ09B0395-0400
Address bus
HWR, LWR
Data bus
BREQ
BACK
φ
RD
AS
Figure 6.21 Example of External Bus Master Operation
T
0
High
(1)
CPU cycles
Minimum 3 cycles
T
Address
1
T
2
(2)
(3)
External bus released
High-impedance
High-impedance
High-impedance
High-impedance
High-impedance
(4)
(5)
(6)
CPU cycles