D13008VXI25V Renesas Electronics America, D13008VXI25V Datasheet - Page 195

• Manufacturer Part Number: D13008VXI25V
• Description: MCU 3V 0K I-TEMP PB-FREE 100-TQF
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13008VXI25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 7 is reserved. It is fixed at 1, and cannot be modified.
• Modes 1 to 4 (Expanded Modes)
Port 6 Data Register (P6DR): P6DR is an 8-bit readable/writable register that stores output data
for port 6. When port 6 functions as an output port, the value of this register is output. For bit 7, a
value of 1 is returned if the bit is read while the PSTOP bit in MSTCRH is cleared to 0, and the
P6 7 pin logic level is returned if the bit is read while the PSTOP bit is set to 1. Bit 7 cannot be
modified. For bits 6 to 0, the pin logic level is returned if the bit is read while the corresponding
bit in P6DDR is cleared to 0, and the P6DR value is returned if the bit is read while the
corresponding bit in P6DDR is set to 1.
P6DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
P6
PSTOP bit in MSTRCH is cleared to 0 (initial value), and an input port if this bit is set to 1.
P6
settings of bits P6
P6
input/output ports. For the method of selecting the pin functions, see table 7.7.
When P6
corresponding P6DDR bit is set to 1, and an input port if this bit is cleared to 0.
7
6
2
functions as the clock output pin (φ) or an input port. P6
to P6
to P6
3
0
2
function as bus control output pins (LWR, HWR, RD, and AS), regardless of the
function as bus control input/output pins (BACK, BREQ, and WAIT) or
to P6
Reserved bit
0
P6
function as input/output ports, the pin becomes an output port if the
⎯
⎯
R
7
1
7
1
6
DDR to P6
7
P6 DDR
R/W
P6
6
W
6
0
6
0
6
3
DDR.
P6 DDR
R/W
P6
5
W
5
0
5
0
5
P6 DDR
Port 6 data direction 6 to 0
These bits select input or output for port 6 pins
Port 6 data 7 to 0
These bits store data for port 6 pins
R/W
P6
4
W
4
0
4
0
4
Rev.4.00 Aug. 20, 2007 Page 149 of 638
P6 DDR
R/W
P6
3
W
3
0
3
0
3
7
is the clock output pin (φ) if the
P6 DDR
R/W
P6
2
W
2
0
2
0
2
P6 DDR
R/W
P6
REJ09B0395-0400
1
W
1
0
1
0
1
7. I/O Ports
P6 DDR
R/W
P6
0
W
0
0
0
0
0