D13008VXI25V Renesas Electronics America, D13008VXI25V Datasheet - Page 360

• Manufacturer Part Number: D13008VXI25V
• Description: MCU 3V 0K I-TEMP PB-FREE 100-TQF
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13008VXI25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

11. Watchdog Timer
11.2.3
RSTCSR is an 8-bit readable and writable register that indicates when a reset signal has been
generated by watchdog timer overflow, and controls external output of the reset signal.
Notes: The method for writing to RSTCSR is different from that for general registers to prevent
Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by
reset signals generated by watchdog timer overflow.
Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that
TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3008 chip
internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to
initialize external system devices. Note that there is no RESO pin in the versions with on-chip
flash memory.
Rev.4.00 Aug. 20, 2007 Page 314 of 638
REJ09B0395-0400
Bit 7
WRST
0
1
Bit
Initial value
Read/Write
inadvertent overwriting. For details see section 11.2.4, Notes on Register Access.
* Only 0 can be written in bit 7, to clear the flag.
[Clearing conditions]
•
•
Reset Control/Status Register (RSTCSR)
Description
[Setting condition]
Set when TCNT overflow generates a reset signal during watchdog timer operation
Reset signal at RES pin.
Read WRST when WRST =1, then write 0 in WRST.
Watchdog timer reset
Indicates that a reset signal has been generated
R/(W)
WRST
7
0
*
Reset output enable
Enables or disables external output of the reset signal
RSTOE
R/W
6
0
⎯
⎯
5
1
⎯
⎯
4
1
Reserved bits
⎯
⎯
3
1
⎯
⎯
2
1
⎯
⎯
1
1
(Initial value)
⎯
⎯
0
1