D13008VXI25V Renesas Electronics America, D13008VXI25V Datasheet - Page 188

• Manufacturer Part Number: D13008VXI25V
• Description: MCU 3V 0K I-TEMP PB-FREE 100-TQF
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13008VXI25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7. I/O Ports
Port
Port 8
Port 9 •
Port A •
Rev.4.00 Aug. 20, 2007 Page 142 of 638
REJ09B0395-0400
Description
•
•
•
5-bit I/O port
P8
schmitt inputs
6-bit I/O port
8-bit I/O port
Schmitt inputs
2
to P8
0
have
Pins
P8
P8
ADTRG
P8
P8
P8
P9
P9
P9
P9
P9
P9
PA
TIOCB
PA
PA
PA
PA
TCLKD
PA
TCLKC
PA
PA
4
3
2
1
0
5
4
3
2
1
0
7
6
5
4
3
2
1
0
/CS
/IRQ
/IRQ
/IRQ
/IRQ
/IRQ
/IRQ
/RxD
/RxD
/TxD
/TxD
/TP
/TP
/TP
/TP
/TP
/TP
/TP
/TP
2
0
7
6
5
4
3
2
1
0
/A
/
/TIOCA
/TIOCB
/TIOCA
/TIOCB
/TIOCA
/TCLKB
/TCLKA
3
2
1
0
5
4
1
0
1
0
/CS
/CS
/CS
/SCK
/SCK
20
1
2
3
/
1
0
2
1
1
0
0
/A
/A
/A
/
/
21
22
23
Expanded Modes
Mode 1
DDR = 0: generic input
DDR = 1 (reset value): CS
IRQ
A/D converter, and generic input
DDR = 0 (after reset): generic input
DDR = 1: CS
IRQ
input
DDR = 0 (after reset): generic input
DDR = 1: CS
IRQ
Input and output (SCK
serial communication interfaces 1 and 0 (SCI1/0), IRQ
and IRQ
Output (TP
grammable timing pattern
controller (TPC), input or
output (TIOCB
timer and generic
input/output
TPC output (TP
(TIOCA
TPC output (TP
(TIOCB
timer input (TCLKD, TCLKC, TCLKB, TCLKA), and
generic input/output
3
2
0
input, CS
and IRQ
input, and generic input/output
2
0
, TIOCB
, TIOCA
4
input, and 6-bit generic input/output
7
) from pro-
1
2
1
output
and CS
1
2
Mode 2
input, CS
) for 16-bit
6
3
output, external trigger input (ADTRG) to
1
0
to TP
to TP
, TIOCA
, TCLKD, TCLKC, TCLKB, TCLKA), 8-bit
3
1
4
0
, SCK
), 16-bit timer input and output
), 16-bit timer input and output
output
2
1
and CS
), and generic input/output
0
output
0
, RxD
Mode 3
Address output (A
3
output, and generic
1
, RxD
0
, TxD
Mode 4
1
, TxD
20
)
0
) for
5