D13008VXI25V Renesas Electronics America, D13008VXI25V Datasheet - Page 185

• Manufacturer Part Number: D13008VXI25V
• Description: MCU 3V 0K I-TEMP PB-FREE 100-TQF
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13008VXI25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

When making a transition to software standby mode, if there is contention with a bus request from
an external bus master, the BACK and strobe states may be indefinite when the transition is made.
When using software standby mode, clear the BRLE bit to 0 in BRCR before executing the
SLEEP instruction.
6.7
6.7.1
ABWCR, ASTCR, WCRH, and WCRL Write Timing: Data written to ABWCR, ASTCR,
WCRH, and WCRL takes effect starting from the next bus cycle. Figure 6.22 shows the timing
when an instruction fetched from area 0 changes area 0 from three-state access to two-state access.
DDR and CSCR Write Timing: Data written to DDR or CSCR for the port corresponding to the
CSn pin to switch between CSn output and generic input takes effect starting from the T
the DDR write cycle. Figure 6.23 shows the timing when the CS
input to CS
BRCR Write Timing: Data written to BRCR to switch between A
generic input or output takes effect starting from the T
shows the timing when a pin is changed from generic input to A
Address bus
Register and Pin Input Timing
Register Write Timing
1
φ
output.
Address bus
φ
CS
1
3-state access to area 0
T
1
Figure 6.22 ASTCR Write Timing
Figure 6.23 DDR Write Timing
T
2
High-impedance
T
3
T
1
P8DDR address
T
1
ASTCR address
3
state of the BRCR write cycle. Figure 6.24
T
T
Rev.4.00 Aug. 20, 2007 Page 139 of 638
2
2
T
23
1
3
2-state access to area 0
, A
pin is changed from generic
23
T
, A
22
3
, A
T
22
1
, A
21
, or A
21
, or A
T
20
REJ09B0395-0400
2
6. Bus Controller
output.
20
output and
3
state of