D13008VXI25V Renesas Electronics America, D13008VXI25V Datasheet - Page 411
D13008VXI25V
Manufacturer Part Number
D13008VXI25V
Description
MCU 3V 0K I-TEMP PB-FREE 100-TQF
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of D13008VXI25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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In transmitting serial data, the SCI operates as follows:
• The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0, the SCI
• After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
• The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI
Figure 12.11 shows an example of SCI transmit operation using a multiprocessor format.
• Receiving Multiprocessor Serial Data: Figure 12.12 shows a sample flowchart for receiving
TDRE
TEND
recognizes that TDR contains new data, and loads this data from TDR into TSR.
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
Serial transmit data is transmitted in the following order from the TxD pin:
⎯ Start bit: One 0 bit is output.
⎯ Transmit data: 7 or 8 bits are output, LSB first.
⎯ Multiprocessor bit: One multiprocessor bit (MPBT value) is output.
⎯ Stop bit(s): One or two 1 bits (stop bits) are output.
⎯ Mark state: Output of 1 bits continues until the start bit of the next transmit data.
loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the
next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop bit,
then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a transmit-
end interrupt (TEI) is requested at this time
multiprocessor serial data and indicates the procedure to follow.
1
TXI interrupt
request
Start
bit
0
TXI interrupt handler
writes data in TDR and
clears TDRE flag to 0
D0
(8-Bit Data with Multiprocessor Bit and One Stop Bit)
Figure 12.11 Example of SCI Transmit Operation
D1
1 frame
Data
D7
processor
Multi-
TXI interrupt
request
bit
0/1
Stop
bit
1
Start
bit
0
Rev.4.00 Aug. 20, 2007 Page 365 of 638
D0
12. Serial Communication Interface
D1
Data
D7
processor
Multi-
bit
0/1
REJ09B0395-0400
request
Stop
bit
TEI interrupt
1
state
Idle (mark)
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