D13008VXI25V Renesas Electronics America, D13008VXI25V Datasheet - Page 453

• Manufacturer Part Number: D13008VXI25V
• Description: MCU 3V 0K I-TEMP PB-FREE 100-TQF
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13008VXI25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

The receive margin can therefore be expressed as follows.
Receive margin in smart card interface mode:
Legend:
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 372)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L =10)
F: Absolute deviation of clock frequency
From the above equation, if F = 0 and D = 0.5, the receive margin is as follows.
When D = 0.5 and F = 0:
Retransmission: Retransmission is performed by the SCI in receive mode and transmit mode as
described below.
• Retransmission when SCI is in Receive Mode
1. If an error is found when the received parity bit is checked, the PER bit is automatically set to
2. The RDRF bit in SSR is not set for the frame in which the error has occurred.
3. If an error is found when the received parity bit is checked, the PER bit is not set to 1 in SSR.
4. If no error is found when the received parity bit is checked, the receive operation is assumed to
5. When a normal frame is received, the data pin is held in three-state at the error signal
Figure 13.12 illustrates retransmission when the SCI is in receive mode.
1. If the RIE bit in SCR is set to the enable state, an ERI interrupt is requested. The PER bit
should be cleared to 0 in SSR before the next parity bit sampling timing.
have been completed normally, and the RDRF bit is automatically set to 1 in SSR. If the RIE
bit in SCR is set to the enable state, an RXI interrupt is requested.
transmission timing.
M = (0.5 −
M = (0.5 – 1/2 × 372) × 100%
= 49.866%
2N
1
) − (L − 0.5) F −
D − 0.5
N
(1 + F) × 100%
Rev.4.00 Aug. 20, 2007 Page 407 of 638
13. Smart Card Interface
REJ09B0395-0400