D13008VXI25V Renesas Electronics America, D13008VXI25V Datasheet - Page 238

• Manufacturer Part Number: D13008VXI25V
• Description: MCU 3V 0K I-TEMP PB-FREE 100-TQF
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13008VXI25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

8. 16-Bit Timer
8.2.5
TISRB is an 8-bit readable/writable register that indicates GRB compare match or input capture
and enables or disables GRB compare match and input capture interrupt requests.
TISRB is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Input Capture/Compare Match Interrupt Enable B2 (IMIEB2): Enables or disables
the interrupt requested by the IMFB2 when IMFB2 flag is set to 1.
Bit 6
IMIEB2
0
1
Rev.4.00 Aug. 20, 2007 Page 192 of 638
REJ09B0395-0400
Initial value
Read/Write
Note: * Only 0 can be written, to clear the flag.
Timer Interrupt Status Register B (TISRB)
Bit
Description
IMIB2 interrupt requested by IMFB2 flag is disabled
IMIB2 interrupt requested by IMFB2 flag is enabled
Reserved bit
⎯
⎯
7
1
IMIEB2
R/W
6
0
IMIEB1
Input capture/compare match interrupt enable B2 to B0
These bits enable or disable interrupts by the IMFB flags
R/W
5
0
IMIEB0
R/W
4
0
Reserved bit
⎯
⎯
3
1
R/(W)*
IMFB2
Input capture/compare match
flags B2 to B0
Status flags indicating GRB
compare match or input capture
2
0
R/(W)*
IMFB1
1
0
R/(W)*
IMFB0
0
0
(Initial value)