D13008VXI25V Renesas Electronics America, D13008VXI25V Datasheet - Page 95

• Manufacturer Part Number: D13008VXI25V
• Description: MCU 3V 0K I-TEMP PB-FREE 100-TQF
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13008VXI25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

2.8.4
Reset Exception Handling: Reset exception handling has the highest priority. The reset state is
entered when the RES signal goes low. Reset exception handling starts after that, when RES
changes from low to high. When reset exception handling starts the CPU fetches a start address
from the exception vector table and starts program execution from that address. All interrupts,
including NMI, are disabled during the reset exception-handling sequence and immediately after it
ends.
Interrupt Exception Handling and Trap Instruction Exception Handling: When these
exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the
program counter and condition code register on the stack. Next, if the UE bit in the system control
register (SYSCR) is set to 1, the CPU sets the I bit in the condition code register to 1. If the UE bit
is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then
Notes: 1.
RES = "High"
Exception-handling state
Exception Handling Operation
Bus-released state
2.
Reset state*
From any state except hardware standby mode, a transition to the reset state occurs
whenever RES goes low.
From any state, a transition to hardware standby mode occurs when STBY goes low.
End of
exception
handling
End of bus
release
1
Bus
request
STBY = "High", RES = "Low"
Figure 2.13 State Transitions
Program execution state
NMI, IRQ , IRQ ,
or IRQ interrupt
Exception
Interrupt source
End of bus release
handling source
Bus request
2
0
1
Rev.4.00 Aug. 20, 2007 Page 49 of 638
SLEEP instruction
with SSBY = 1
SLEEP
instruction
with SSBY = 0
Hardware standby mode*
Software standby mode
Power-down state
Sleep mode
REJ09B0395-0400
2
2. CPU