D13008VXI25V Renesas Electronics America, D13008VXI25V Datasheet - Page 166

• Manufacturer Part Number: D13008VXI25V
• Description: MCU 3V 0K I-TEMP PB-FREE 100-TQF
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13008VXI25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6. Bus Controller
Output of CS
register (CSCR). A reset leaves pins CS
to CS
When the on-chip ROM, on-chip RAM, and internal I/O registers are accessed, CS
high. The CS
signals for SRAM and other devices.
6.3.5
The H8/3008 provides a choice of two address update methods: either the same method as in the
previous H8/300H Series (address update mode 1), or a method in which address updating is
restricted to external space accesses (address update mode 2).
Figure 6.5 shows examples of address output in these two update modes.
Address bus
(Address update
mode 1)
Address bus
(Address update
mode 2)
RD
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REJ09B0395-0400
7
, the corresponding CSCR bits must be set to 1. For details, see section 7, I/O Ports.
Address Output Method
n
Figure 6.5 Sample Address Output in Each Address Update Mode
4
signals are decoded from the address signals. They can be used as chip select
to CS
Address bus
memory cycle
7
: Output of CS
CS
On-chip
Figure 6.4 CSn Signal Output Timing (n = 0 to 7)
φ
n
(Basic Bus Interface, 3-State Space)
4
read cycle
to CS
External
4
to CS
7
is enabled or disabled in the chip select control
External address in area n
7
in the input state. To output chip select signals CS
memory cycle
On-chip
read cycle
External
0
to CS
memory cycle
On-chip
7
remain
4