D13008VXI25V Renesas Electronics America, D13008VXI25V Datasheet - Page 498

• Manufacturer Part Number: D13008VXI25V
• Description: MCU 3V 0K I-TEMP PB-FREE 100-TQF
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13008VXI25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

17. Clock Pulse Generator
External Clock: The external clock frequency should be equal to the system clock frequency
when not divided by the on-chip frequency divider. Table 17.3 shows the clock timing, figure 17.6
shows the external clock input timing, and figure 17.7 shows the external clock output settling
delay timing. When the appropriate external clock is input via the EXTAL pin, its waveform is
corrected by the on-chip oscillator and duty adjustment circuit.
When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the
on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to external
devices after the external clock settling time (t
must remain reset with the reset signal low during t
Table 17.3 Clock Timing (Preliminary)
Item
External clock input low
pulse width
External clock input high
pulse width
External clock rise time
External clock fall time
Clock high pulse width
External clock output
settling delay time
Note:
Rev.4.00 Aug. 20, 2007 Page 452 of 638
REJ09B0395-0400
Clock low pulse width
* t
DEXT
includes a RES pulse width (t
Symbol Min
t
t
t
t
t
t
t
EXL
EXH
EXr
EXf
CL
CH
DEXT
*
V
to 3.6 V
15
15
⎯
⎯
0.4
80
500
0.4
80
CC
= 3.0 V
Max
⎯
⎯
5
5
0.6
⎯
⎯
RESW
0.6
⎯
DEXT
). t
) has passed after the clock input. The system
RESW
DEXT
, while the clock output is unstable.
V
±10 %
Min
15
15
⎯
⎯
0.4
80
500
0.4
80
= 20 t
CC
= 5.0 V
cyc
Max
⎯
⎯
5
5
0.6
⎯
⎯
0.6
⎯
Unit
ns
ns
ns
μs
ns
ns
t
ns
t
cyc
cyc
Test Conditions
Figure 17.6
φ ≥ 5 MHz
φ < 5 MHz
φ ≥ 5 MHz
φ < 5 MHz
Figure 17.7
Figure
19.7