EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 106

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Clock Networks and PLLs in Cyclone III Devices
6–6
Cyclone III Device Handbook, Volume 1
Clock Control Block
The clock control block drives global clock networks. Clock control blocks
are located on each side of the device, close to the dedicated clock input
pins. Global clock networks are optimized for minimum clock skew and
delay.
Table 6–3
turn feeds the global clock networks.
In Cyclone III devices, the dedicated clock input pins, PLL counter
outputs, dual-purpose clock I/O inputs, and internal logic can all feed the
clock control block for each global clock network. The output from the
clock control block in turn feeds the corresponding global clock network.
This global clock can drive the PLL input if the clock control block inputs
are outputs of another PLL or dedicated clock input pins. The clock
control blocks are at the device periphery and there are a maximum of 20
clock control blocks available per Cyclone III device.
Dedicated clock inputs
Dual-purpose clock
(
I/O inputs
PLL outputs
Internal logic
DPCLK
Table 6–3. Clock Control Block Inputs
and
lists the sources that can feed the clock control block, which in
CDPCLK)
Input
Dedicated clock input pins can drive clocks or
global signals, such as synchronous and
asynchronous clears, presets, or clock enables
onto given global clock networks.
DPCLK
dual function pins that can be used for high fan-
out control signals, such as protocol signals,
TRDY
DDR, via the global clock network. Clock
control blocks which have inputs driven by
internal logic will not be able to drive PLL
inputs.
The PLL counter outputs can drive the global
clock network.
You can drive the global clock network through
the logic array routing to enable internal logic
(Logic Elements) to drive a high fan-out, low
skew signal path. Clock control blocks which
have inputs driven by internal logic will not be
able to drive PLL inputs.
and
and
IRDY
CDPCLK
Altera Corporation- Preliminary
Description
signals for PCI, or
I/O pins are bidirectional
March 2007
DQS
for