EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 164

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Cyclone III Device I/O Features
7–12
Cyclone III Device Handbook, Volume 1
f
f
f
Refer to the Assignment Editor chapter in volume 2 of the Quartus II
Handbook for more information about how to set the open-drain output
feature.
Bus Hold
Each Cyclone III device user I/O pin provides an optional bus-hold
feature. The bus-hold circuitry holds the signal on an I/O pin at its
last-driven state. Since the bus-hold feature holds the last-driven state of
the pin until the next input signal is present, an external pull-up or
pull-down resistor is not necessary to hold a signal level when the bus is
tri-stated.
The bus-hold circuitry also pulls undriven pins away from the input
threshold voltage where noise can cause unintended high-frequency
switching. You can select this feature individually for each I/O pin. The
bus-hold output drives no higher than V
signals.
1
The bus-hold circuitry is only active after configuration. When going into
user mode, the bus-hold circuit captures the value on the pin present at
the end of configuration.
Refer to the Assignment Editor chapter in volume 2 of the Quartus II
Handbook for more information about how to set the bus hold feature.
Refer to the DC and Switching Characteristics chapter in volume 2 of the
Cyclone III Device Handbook, for the specific sustaining current for each
V
current used to identify the next driven input level.
Programmable Pull-Up Resistor
Each Cyclone III device I/O pin provides an optional programmable
pull-up resistor while in user mode. If you enable this feature for an I/O
pin, the pull-up resistor holds the output to the V
pin's bank.
CCIO
voltage level driven through the resistor and for the overdrive
If you enable the bus-hold feature, the device cannot use the
programmable pull-up option. Disable the bus-hold feature
when the I/O pin is configured for differential signals. Bus-hold
circuitry is not available on the dedicated clock pins.
CCIO
Altera Corporation-Preliminary
to prevent overdriving
CCIO
level of the output
March 2007