EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 124

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Clock Networks and PLLs in Cyclone III Devices
Figure 6–14. Phase Relationship Between PLL Clocks in Zero Delay Buffer Mode
Hardware
Features
6–24
Cyclone III Device Handbook, Volume 1
External PLL Clock
Output at the Output Pin
PLL Clock at the
Register Clock Port
Figure 6–14
relationship in ZDB mode.
Cyclone III PLLs support a number of features for general-purpose clock
management. This section discusses clock multiplication and division
implementation, phase-shifting implementations and programmable
duty cycles.
Clock Multiplication and Division
Each Cyclone III PLL provides clock synthesis for PLL output ports using
m/(n*post-scale counter) scaling factors. The input clock is divided by a
pre-scale factor, n, and is then multiplied by the m feedback factor. The
control loop drives the VCO to match f
unique post-scale counter that divides down the high-frequency VCO.
For multiple PLL outputs with different frequencies, the VCO value is the
least common multiple of the output frequencies that meets its frequency
specifications. For example, if output frequencies required from one PLL
are 33 and 66 MHz, then the Quartus II software sets the VCO to 660 MHz
(the least common multiple of 33 and 66 MHz within the VCO range).
Then, the post-scale counters scale down the VCO frequency for each
output port.
There is one pre-scale counter, n, and one multiply counter, m, per PLL,
with a range of 1 to 512 for both m and n. The n counter does not use duty
cycle control since the purpose of this counter is only to calculate
frequency division. There are five generic post-scale counters per PLL
PLL inclk
Phase Aligned
shows an example waveform of the PLL clocks' phase
in
(m/n). Each output port has a
Altera Corporation- Preliminary
March 2007