EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 58

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Memory Blocks in Cyclone III Devices
Figure 4–1. M9K Control Signal Selection
4–4
Cyclone III Device Handbook, Volume 1
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Dedicated
Row LAB
Clocks
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6
clock_a
Parity Bit Support
Parity checking for error detection is possible by using the parity bit along
with internal logic resources. Cyclone III M9K memory blocks support a
parity bit for each storage byte. You can use this bit optionally as a parity
bit or as an additional data bit. No parity function is actually performed
on this bit.
Byte Enable Support
Cyclone III M9K memory blocks support byte enables that mask the input
data so that only specific bytes of data are written. The unwritten bytes
retain the previous written value. The write enable (wren) signals, along
with the byte enable (byteena) signals, control the RAM block's write
operations. The default value for the byte-enable signals is high
clock_b
clocken_a
clocken_b
rden_a
rden_b
wren_a
wren_b
Altera Corporation-Preliminary
aclr_a
aclr_b
addressstall_a
addressstall_b
March 2007
byteena_a
byteena_b