EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 154

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Cyclone III Device I/O Features
Cyclone III
I/O Element
Figure 7–1. Cyclone III IOE Structure
Note to
(1)
7–2
Cyclone III Device Handbook, Volume 1
There are two paths available for combinational or registered inputs to the logic array. Each path contains a unique
programmable delay chain.
Figure
Logic Array
7–1:
CLK_Out
Output B
Output A
Input (1)
CLK_In
OE
Cyclone III device IOEs contain a bidirectional I/O buffer and five
registers for complete embedded bidirectional single-data rate transfer.
Figure 7–1
input register, two output registers, and two output-enable registers. The
two output registers and two output-enable registers are utilized for
double-data rate (DDR) applications. You can use the input registers for
fast setup times and the output registers for fast clock-to-output times.
Additionally, you can use the output-enable (OE) registers for fast
clock-to-output enable timing. You can use IOEs for input, output, or
bidirectional data paths.
Output Register
Output Register
D
D
shows the Cyclone III IOE structure. The IOE contains one
Q
Q
OE Register
OE Register
D
D
Q
Q
Input Register
D
Q
Altera Corporation-Preliminary
March 2007