EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 429

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Cyclone III Device Datasheet: DC & Switching Characteristics
Altera Corporation-Preliminary
March 2007
Note to
(1)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
JCP
JCH
JCL
JPSU_TDI
JPSU_TMS
JPH
JPCO
JPZX
JPXZ
JSSU
JSH
JSCO
JSZX
JSXZ
Table 1–24. Cyclone III JTAG Timing Parameters
Symbol
The specification is shown for 3.3 V, 3.0 V and 2.5 V LVTTL/LVCMOS operation of JTAG pins. For 1.8- V
LVTTL/LVCMOS and 1.5- V LVCMOS, the JTAG port/capture register clock setup time is 3 ns and port clock to
output time is 15 ns.
Table
1–24:
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time for
JTAG port setup time for TMS
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
Table 1–23
Table 1–24
For more information, see
Active Parallel (AP)
Active Serial (AS)
Table 1–23. Cyclone III Active Configuration Mode
Specifications
Programming Mode
TDI(1)
(1)
lists the Cyclone III Active Configuration Mode Specifications
shows the JTAG timing parameters and values for Cyclone III.
(1)
Parameter
(1)
(1)
(1)
”JTAG Waveform”
DCLK Range
20 - 40
20 - 40
at ”Glossary”.
Min
40
20
20
10
10
1
3
5
Cyclone III Handbook
Max
15
15
15
25
25
25
Preliminary
Preliminary
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1–19
.