EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 207

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Figure 8–17. LVPECL I/O Interface
Altera Corporation-Preliminary
March 2007
LVPECL Transmitter
f
Figure 8–17
Differential SSTL I/O Standard Support in Cyclone III Devices
The differential SSTL I/O standard is a memory-bus standard used for
applications such as high-speed double-data rate (DDR) SDRAM
interfaces. The differential SSTL I/O standard AC and DC specifications
are similar to SSTL single-ended specifications. The standard requires
two differential inputs with an external reference voltage (V
an external termination voltage (V
resistors are connected. Cyclone III devices support differential SSTL-2
and SSTL-18 I/O standards. A 2.5-V output source voltage is required for
differential SSTL-2, and a 1.8-V output source voltage is required for
differential SSTL-18. The differential SSTL output standard is only
supported at PLL#_CLKOUT pins using two single-ended SSTL output
buffers (PLL#_CLKOUTp and PLL#_CLKOUTn) programmed to have
opposite polarity.
1
For SSTL signaling characteristics, see the Cyclone III Device I/O Features
chapter and the Cyclone III Device Datasheet: DC and Switching
Characteristics of Cyclone III Devices chapter in volumes 1 and 2,
respectively, of the Cyclone III Device Handbook.
The differential SSTL input standard is supported at the global
clock (GCLK) pins only, where it treats differential inputs as two
single-ended SSTL and only decodes one of them.
shows the LVPECL I/O interface.
50 Ω
50 Ω
TT
Cyclone III Device Handbook, Volume 1
) of 0.5 x V
100 Ω
High-Speed I/O Standards Support
CCIO
Cyclone III Device
LVPECL Receiver
to which termination
REF
) as well as
8–17