EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 37

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Figure 2–5. LE in Arithmetic Mode
Altera Corporation-Preliminary
March 2007
of previous LE)
cin (from cout
data4
data1
data2
data3
Packed Register Input
The Quartus II Compiler automatically creates carry chain logic during
design processing, or you can create it manually during design entry.
Parameterized functions such as LPM functions automatically take
advantage of carry chains for the appropriate functions.
The Quartus II Compiler creates carry chains longer than 16 LEs by
automatically linking LABs in the same column. For enhanced fitting, a
long carry chain runs vertically, which allows fast horizontal connections
to M9K memory blocks or embedded multipliers through direct link
interconnects. For example, if a design has a long carry chain in a LAB
column next to a column of M9K memory blocks, any LE output can feed
an adjacent M9K memory block through the direct link interconnect.
Whereas if the carry chains ran horizontally, any LAB not next to the
column of M9K memory blocks would use other row or column
interconnects to drive a M9K memory block. A carry chain continues as
far as a full column.
Three-Input
Three-Input
LUT
LUT
cout
Register chain
connection
Register Bypass
clock (LAB Wide)
(LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
sload
(LAB Wide)
sclear
Register Feedback
Cyclone III Device Handbook, Volume 1
ENA
D
CLRN
Q
LE Operating Modes
Row, column, and
direct link routing
Row, column, and
direct link routing
Local routing
Register
chain output
2–7