EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 160

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EP3C16F256I7N

Manufacturer Part Number
EP3C16F256I7N
Description
Cyclone III
Manufacturer
Altera
Datasheets

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Cyclone III Device I/O Features
Figure 7–6. Cyclone III IOE in Bidirectional I/O Configuration
I/O Element
Features
7–8
Cyclone III Device Handbook, Volume 1
Interconnect
Column
or Row
io_clk[5..0]
data_in1
data_in0
Chip-Wide Reset
OE
clkout
aclr/prn
oe_out
oe_in
Programmable Current Strength
The output buffer for each Cyclone III device I/O pin has a
programmable current strength control for certain I/O standards. The
LVTTL, LVCMOS, SSTL-2 Class I and II, SSTL-18 Class I and II, HSTL-18
Class I and II, HSTL-15 Class I and II, and HSTL-12 Class I and II
standards have several levels of current strength that you can control.
clkin
preset
sclr/
OE Register
Output Register
ENA
ENA
D
D
ACLR
/PRN
ACLR
/PRN
Q
Q
Input Register
ENA
D
ACLR
/PRN
Current Strength Control
Q
Slew Rate Control
Open-Drain Out
Pin Delay
Output
Input Register
or Input Pin to
Logic Array
Input Pin to
Delay
Delay
Altera Corporation-Preliminary
V
CCIO
V
CCIO
March 2007
Programmable
Resistor
Pull-Up
Bus Hold

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