EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 184

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Cyclone III Device I/O Features
Pad Placement
and DC
Guidelines
7–32
Cyclone III Device Handbook, Volume 1
f
f
f
You can use I/O pins and internal logic to implement the LVDS I/O
receiver and transmitter in Cyclone III devices. Cyclone III devices do not
contain dedicated serialization or de-serialization circuitry. Therefore,
shift registers, internal PLLs, and IOEs are used to perform
serial-to-parallel conversions on incoming data and parallel-to-serial
conversion on outgoing data.
The LVDS standard does not require an input reference voltage, but it
does require a 100-Ω termination resistor between the two signals at the
input buffer. An external resistor network is required on the transmitter
side for top and bottom I/O banks.
For more information about Cyclone III high-speed differential interface
support, refer to the High-Speed Differential Interfaces in Cyclone III Devices
chapter in volume 1 of the Cyclone III Device Handbook.
External Memory Interfacing
Cyclone III devices support I/O standards required to interface with a
broad range of external memory interfaces such as DDR SDRAM, DDR2
SDRAM, and QDRII SRAM.
For more information about Cyclone III external memory interface
support, refer to the External Memory Interfaces in Cyclone III Devices
chapter in volume 1 of the Cyclone III Device Handbook.
This section provides pad placement guidelines for the programmable
I/O standards supported by Cyclone III devices and includes essential
information for designing systems using the devices' selectable I/O
capabilities. This section also discusses DC limitations and guidelines.
Quartus II software provides user-controlled restriction relaxation
options for some placement constraints. When you relax a default
restriction, the Quartus II fitter generates warnings.
For more information about how Quartus II software checks I/O
restrictions, see the I/O Management chapter in the Quartus II Handbook.
Differential Pad Placement Guidelines
To maintain an acceptable noise level on the V
restrictions on placement of single-ended I/O pads in relation to
differential pads. Use the following guidelines for placing single-ended
pads with respect to differential pads and for differential output pads
placement in Cyclone III devices.
Altera Corporation-Preliminary
CCIO
supply, there are
March 2007