EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 368

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

SEU Mitigation in Cyclone III Devices
Error Detection
Timing
13–6
Cyclone III Device Handbook, Volume 1
Register
32-bit signature register
32-bit storage register
Table 13–3. Error Detection Registers
Table 13–4. Minimum and Maximum Error Detection Frequencies
Device Type
Cyclone III
Error Detection
Frequency
80 MHz/2
This register contains the CRC signature. The signature register contains the result
of the user mode calculated CRC value compared against the pre-calculated CRC
value. If no errors are detected, the signature register is all zeros. A non-zero
signature register indicates an error in the configuration CRAM contents.
The
This register is loaded with the 32-bit pre-computed CRC signature at the end of the
configuration stage. The signature is then loaded into the 32-bit CRC circuit (called
the Compute & Compare CRC block, as shown in
calculate the CRC error. This register forms a 32-bit scan chain during execution of
the
change the content of the storage register. Therefore, the functionality of the error
detection CRC circuitry is checked in-system by executing the instruction to inject an
error during the operation. The operation of the device is not halted when issuing the
CHANGE_EDREG
Table 13–3
When the error detection CRC feature is enabled through the Quartus II
software, the device automatically activates the CRC process upon
entering user mode, after configuration and initialization is complete.
The CRC_ERROR pin is driven low until the error detection circuitry has
detected a corrupted bit in the previous CRC calculation. Once the pin
goes high, it remains high during the next CRC calculation. This pin does
not log the previous CRC calculation. If the new CRC calculation does not
contain any corrupted bits, the CRC_ERROR pin is driven low. The error
detection runs until the device is reset.
The error detection circuitry runs off an internal configuration oscillator
with a divisor that sets the maximum frequency.
minimum and maximum error detection frequencies.
n
CHANGE_EDREG
CRC_ERROR
Detection Frequency
Maximum Error
defines the registers shown in
80 MHz
instruction.
signal is derived from the contents of this register.
JTAG instruction. The
Detection Frequency
Function
Minimum Error
312.5 kHz
CHANGE_EDREG
Figure
Figure
Altera Corporation-Preliminary
13–1) during user mode to
13–1.
Table 13–4
0, 1, 2, 3, 4, 5, 6, 7, 8
JTAG instruction can
Valid Divisors (2
shows the
March 2007
n
)