EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 122

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Clock Networks and PLLs in Cyclone III Devices
Figure 6–12. Phase Relationship between PLL Clocks in No Compensation Mode
Notes to
(1)
(2)
6–22
Cyclone III Device Handbook, Volume 1
Internal clocks fed by the PLL are phase-aligned to each other.
The PLL clock outputs can lead or lag the PLL input clocks.
Figure
6–12:
The source-synchronous mode compensates for delay of the clock
network used plus any difference in the delay between these two paths:
■
■
1
No Compensation Mode
In the no compensation mode, the PLL does not compensate for any clock
networks. This provides better jitter performance because the clock
feedback into the PFD does not pass through as much circuitry. Both the
PLL internal and external clock outputs are phase shifted with respect to
the PLL clock input.
relationship of the PLL clock in this mode.
Data pin to I/O element register input
Clock input pin to the PLL PFD input
Set the input pin to the register delay chain within the I/O
element to zero in the Quartus II software for all data pins
clocked by a source-synchronous mode PLL. Also, all data pins
must use the PLL COMPENSATED logic option in the
Quartus II software.
Figure 6–12
shows a waveform example of the phase
Altera Corporation- Preliminary
Notes
(1),
(2)
March 2007