EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 107

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Figure 6–1. Clock Control Block
Notes to
(1)
(2)
(3)
(4)
Altera Corporation-Preliminary
March 2007
CLK[n + 3]
CLK[n + 2]
CLK[n + 1]
CLK[n]
The clkswitch signal can either be set through the configuration file or dynamically set when using the manual
PLL switchover feature. The output of the multiplexer is the input clock (fIN) for the PLL.
The clkselect[1..0] signals are fed by internal logic and can be used to dynamically select the clock source for
the global clock network when the device is in user mode.
The static clock select signals are set in the configuration file. Therefore, dynamic control when the device is in user
mode is not feasible.
You can use internal logic to enable or disable the global clock network in user mode.
Figure
6–1:
inclk1
inclk0
Static Clock Select (3)
CLKSWITCH (1)
The control block has two functions:
■
■
Figure 6–1
Each PLL generates five clock outputs through the c[4..0] counters.
Two of these clocks can drive the global clock network through a clock
control block as shown in
Notes
Dynamic global clock network clock source selection
Global clock network power-down (dynamic enable and disable)
f
IN
DPCLK or CDPCLK
(1), (2), (3),
shows the clock control block.
PLL
Internal Logic
C0
C1
C2
C3
C4
(4)
Figure
CLKSELECT[1..0] (2)
6–1.
Cyclone III Device Handbook, Volume 1
Clock Control Block
Static Clock
Select (3)
Internal Logic (4)
Enable/
Disable
Clock Networks
Global
Clock
6–7