EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 146

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Clock Networks and PLLs in Cyclone III Devices
Figure 6–26. PLL Dynamic Phase Shift
6–46
Cyclone III Device Handbook, Volume 1
Use the following procedure to perform one dynamic phase shift step:
1.
2.
3.
4.
5.
6.
All signals are synchronous to scanclk, so they will be latched on the
scanclk edges and must meet tsu/th requirements with respect to the
scanclk edges.
Dynamic phase shifting can be repeated indefinitely. All signals are
synchronous to scanclk, so they must meet tsu/th requirements with
respect to scanclk edges.
The phasestep signal is latched on the negative edge of scanclk. In
Figure
Phasestep must stay high for at least two scanclk cycles. On the
second scanclk rising edge after phasestep is latched (indicated by the
fourth rising edge), the values of phaseupdown and
phasecounterselect are latched and the PLL starts dynamic phase
shifting for the specified counter(s) and in the indicated direction. On the
fourth scanclk rising edge, phasedone goes high to low and remains
Set phaseupdown and phasecounterselect as required.
Assert phasestep. Each phasestep pulse enables one phase shift.
The phasestep pulses must be at least one scanclk cycle apart.
Wait for phasedone to go low.
De-assert phasestep.
Wait for phasedone to go high.
Repeat steps 1 through 5 as many times as required to get multiple
phase shifts.
6–26, this is shown by the second scanclk falling edge.
Altera Corporation- Preliminary
March 2007