EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 578

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Glossary
1–168
Cyclone III Handbook
Letter
Table 1–104. Glossary
O
Q
N
P
R
S
PLL Block
R
RSKM (Receiver
input skew margin)
Single-ended
Voltage referenced
I/O Standard
SW (Sampling
Window)
L
Term
—
—
—
The following block diagram highlights the PLL Specification parameters.
Receiver differential input discrete resistor (external to Cyclone III device).
HIGH-SPEED I/O Block: The total margin left after accounting for the sampling
window and TCCS. RSKM = (TUI - SW - TCCS) / 2.
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and
DC input signal values. The AC values indicate the voltage levels at which the
receiver must meet its timing specifications. The DC values indicate the voltage
levels at which the final logic state of the receiver is unambiguously defined. Once
the receiver input has crossed the AC value, the receiver will change to the new
logic state. The new logic state will then be maintained as long as the input stays
beyond the DC threshold. This approach is intended to provide predictable
receiver timing in the presence of input waveform ringing.
HIGH-SPEED I/O Block: The period of time during which the data must be valid in
order to capture it correctly. The setup and hold times determine the ideal strobe
position within the sampling window.
Core Clock
Key
CLK
V
V
OH
OL
Reconfigurable in User Mode
Switchover
f
IN
N
f
INPFD
Definitions
V
PFD
REF
—
—
—
M
CP
Altera Corporation- Preliminary
Phase tap
LF
VCO
f
VCO
V
V
IH(DC)
IL(DC)
Counters
C0..C4
CLKOUT Pins
V
V
IH ( AC )
IL(AC )
March 2007
f
f
OUT_EXT
OUT
V
CCIO
V
GCLK
SS