EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 383
EP3C16F256I7N
Manufacturer Part Number
EP3C16F256I7N
Description
Cyclone III
Manufacturer
Altera
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Altera Corporation-Preliminary
March 2007
Notes to
(1)
(2)
SignalTap II
instructions
Table 14–4. Cyclone III JTAG Instructions
Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
For more information on how to use CONFIG_IO, ACTIVE_DISENGAGE, ACTIVE_ENGAGE and
APFC_BOOT_ADDR instructions for Cyclone III devices, refer to the Configuring Cyclone III Devices chapter of the
Cyclone III Device Handbook.
JTAG Instruction
Table
14–4:
Instruction Code
The IEEE Std. 1149.1 TAP controller, a 16-state state machine clocked on
the rising edge of TCK, uses the TMS pin to control IEEE Std. 1149.1
operation in the device.
machine.
Monitors internal device operation with the SignalTap II
embedded logic analyzer.
Figure 14–5
IEEE Std. 1149.1 BST Operation Control
Cyclone III Device Handbook, Volume 1
shows the TAP controller state
Description
14–9
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