EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 367
EP3C16F256I7N
Manufacturer Part Number
EP3C16F256I7N
Description
Cyclone III
Manufacturer
Altera
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Figure 13–1. Error Detection Block Diagram
Altera Corporation-Preliminary
March 2007
Error Detection
State Machine
32-bit Storage
Register
This section focuses on the first type, the 32-bit CRC when the device is in
user mode.
Error Detection Registers
There are two sets of 32-bit registers in the error detection circuitry that
store the computed CRC signature and precalculated CRC value. A
non-zero value on the signature register causes the CRC_ERROR pin to set
high.
and the two related 32-bit registers: the signature register and the storage
register.
During configuration, after a frame of data has loaded into the
device, the pre-computed CRC is shifted into the CRC circuitry.
Simultaneously, the CRC value for the data frame shifted-in is
calculated. If the pre-computed CRC and calculated CRC values do
not match, nSTATUS is set low. Every data frame has a 16-bit CRC,
and therefore, there are many 16-bit CRC values for the whole
configuration bit stream. Every device has a different length of the
configuration data frame.
Figure 13–1
32
Control Signals
shows the block diagram of the error detection block
Compute & Compare
32-bit Signature
Cyclone III Device Handbook, Volume 1
Register
CRC
32
32
Error Detection Block
13–5
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