EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 60

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Memory Blocks in Cyclone III Devices
Figure 4–2. Cyclone III Byte Enable Functional Waveform
Note to
(1)
4–6
Cyclone III Device Handbook, Volume 1
For this functional waveform, “New Data” mode is selected.
contents at a0
contents at a1
contents at a2
q (asynch)
Figure
address
inclock
byteena
rden
wren
data
4–2:
XXXX
XX
an
FFFF
doutn
FFFF
Figure 4–2
operations of the RAM.
When a byte-enable bit is de-asserted during a write cycle, the old data in
the memory appears in the corresponding data-byte output. When a byte-
enable bit is asserted during a write cycle, the corresponding data-byte
output depends on the setting chosen in the Quartus
be either the newly written data or the old data at that location.
Packed Mode Support
Cyclone III M9K memory blocks support packed mode. You can
implement two single-port memory blocks in a single block under the
following conditions:
■
■
a0
10
FFFF
Each of the two independent block sizes is less than or equal to half
of the M9K block size. The maximum data width for each
independent block is 18-bits wide.
Each of the single-port memory blocks is configured in single-clock
mode.
ABFF
shows how the wren and byteena signals control the
ABCD
a1
01
FFCD
11
a2
(1)
ABCD
ABFF
a0
FFCD
ABFF
Altera Corporation-Preliminary
ABCD
a1
XXXX
XX
FFCD
®
II software. It can
a2
March 2007
ABCD