EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 108
EP3C16F256I7N
Manufacturer Part Number
EP3C16F256I7N
Description
Cyclone III
Manufacturer
Altera
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Clock Networks and PLLs in Cyclone III Devices
Figure 6–2. EP3C16 and Larger PLL, CLK[], DPCLK[] and Clock Control Block Locations
Notes to
(1)
(2)
6–8
Cyclone III Device Handbook, Volume 1
CDPCLK0
CDPCLK1
CLK[3..0]
DPCLK1
DPCLK0
There are five clock control blocks on each side.
Only one of the corner
pins can be used as general-purpose I/O pins.
Figure
4
6–2:
PLL
PLL
4
1
3
CDPCLK
5
CDPCLK2
CDPCLK7
Global Clock Network Clock Source Generation
There are a total of ten clock control blocks in the smaller Cyclone III
devices (EP3C5 and EP3C10), and a total of 20 clock control blocks in the
larger Cyclone III devices (EP3C16 devices and larger).
Figure 6–3
block location for different device densities.
(2)
(2)
pins in each corner can feed the clock control block at a time. The other
Clock Control
2
2
4
Block (1)
show the Cyclone III PLL, clock inputs and the clock control
GCLK[19..0]
5
DPCLK[11.10]
DPCLK[3..2]
20
2
2
CLK[15..12]
CLK[11..6]
20
20
4
4
DPCLK[9..8]
DPCLK[5..4]
20
GCLK[19..0]
Clock Control
2
2
Block (1)
Remote clock from
two clock pins at
adjacent edge of
device
2
4
2
5
CDPCLK6
CDPCLK3
Altera Corporation- Preliminary
(2)
(2)
5
PLL
PLL
4
2
4
Note (1)
Figure 6–2
4
March 2007
CDPCLK5
DPCLK7
CLK[7..4]
DPCLK6
CDPCLK4
CDPCLK
and
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