EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 114

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EP3C16F256I7N

Manufacturer Part Number
EP3C16F256I7N
Description
Cyclone III
Manufacturer
Altera
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Clock Networks and PLLs in Cyclone III Devices
6–14
Cyclone III Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
Loss of lock detection
Table 6–5. Cyclone III PLL Hardware Features (Part 2 of 2)
C counters range from 1 through 512 if the output clock uses a 50% duty cycle. For any output clocks using a non-
50% duty cycle, the post-scale counters range from 1 through 256.
Provided input clock jitter is within input jitter tolerance specifications.
The smallest phase shift is determined by the VCO period divided by eight. For degree increments, the Cyclone III
device can shift all output frequencies in increments of at least 45 degrees. Smaller degree increments are possible
depending on the frequency and divide parameters.
Table
6–5:
Hardware Features
Figure 6–7
shows the location of PLLs in Cyclone III devices.
Yes
Altera Corporation- Preliminary
Availability
March 2007

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