EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 178

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Cyclone III Device I/O Features
Figure 7–13. Cyclone III Differential SSTL I/O Standard Termination
I/O Banks
7–26
Cyclone III Device Handbook, Volume 1
Termination
External
On-Board
Termination
OCT
Cyclone III
Series OCT
Transmitter
Transmitter
f
50 Ω
25 Ω
25 Ω
Differential SSTL Class I
For information on Cyclone III differential PPDS, LVDS, mini LVDS, and
RSDS I/O standard termination, refer to the High-Speed Differential
Interfaces in Cyclone III Devices chapter of the Cyclone III Device Handbook.
The I/O pins on Cyclone III devices are grouped together into I/O banks,
and each bank has a separate power bus. All Cyclone III devices have
eight I/O banks, as shown in
associated with one I/O bank. All single-ended and differential I/O
standards are supported in all banks except HSTL-12 class II, which is
only supported in column I/O banks.
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
V TT
V TT
50 Ω
50 Ω
V TT
V TT
Receiver
Receiver
Cyclone III
Series OCT
25 Ω
Transmitter
Transmitter
Figure
Differential SSTL Class II
7–14. Each device I/O pin is
V TT
50 Ω
25 Ω
25 Ω
50 Ω
V TT V TT
Altera Corporation-Preliminary
V TT
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
V TT
V TT V TT
50 Ω
V TT
50 Ω
March 2007
Receiver
Receiver