EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 337

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Figure 11–2. Transistor Level Diagram of FPGA Device I/O Buffers
Note to
(1)
(2)
Power-On Reset
Circuitry
Altera Corporation-Preliminary
March 2007
This is the logic array signal or the larger of either the V
This is the larger of either the V
Figure
11–2:
n+
Logic Array
Cyclone III devices contain POR circuitry to keep the device in a reset
state until the power supply voltage levels have stabilized during
power-up. The POR circuit monitors the V
tri-states all user I/O pins until the V
operating levels. In addition, the POR circuitry also ensures the V
level of I/O banks 1, 6, 7, and 8 that contains configuration pins reach an
acceptable level before configuration is triggered.
After the Cyclone III device enters user mode, the POR circuit continues
to monitor the V
user mode can be detected. If the V
POR trip point during user mode, the POR circuit resets the device. If the
V
device.
Wake-Up Time for Cyclone III Devices
In some applications, it may be necessary for a device to wake up very
quickly in order to begin operation. The Cyclone III device offers the
Fast-On feature to support fast wake-up time applications. For
Cyclone III devices, MSEL[3..0] pin settings determine the POR time
(t
standard POR ranges from 50 ms to 200 ms.
p-well
Signal
POR
CCIO
CCIO
) of the device. The fast POR ranges from 3 ms to 9 ms while the
voltage sags during user mode, the POR circuit does not reset the
or V
n+
PAD
signal.
CCINT
V
Hot Socketing and Power-On Reset in Cyclone III Devices
PAD
and V
CCIO
p+
or V
CCA
PAD
pin so that a brown-out condition during
(1)
signal.
CCINT
Cyclone III Device Handbook, Volume 1
CC
n-well
V
reaches the recommended
and V
CCIO
p+
CCINT
CCA
, V
(2)
n+
CCIO
voltage sags below the
p-substrate
, and V
CCA
pin and
CCIO
11–5