EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 387

• Manufacturer Part Number: EP3C16F256I7N
• Description: Cyclone III
• Manufacturer: Altera

Figure 14–8. IEEE Std. 1149.1 BST SAMPLE/PRELOAD Mode
Altera Corporation-Preliminary
March 2007
Capture Phase:
In the capture phase, the signals at
the pin, OEJ and OUTJ are loaded
into the capture registers. The
CLOCK signals are supplied by the
TAP controller's CLOCKDR output.
The data retained in these
registers consists of signals from
normal device operation.
Shift & Update Phases
In the shift phase, the previously
captured signals at the pin OEJ
and OUTJ, are shifted out of the
boundary-scan register via the
TDO pin using CLOCK. As data
is shifted out the patterns for the
next test can be shifted in via the
TDI pin.
In the update phase, data is
transferred from the capture
to the UPDATE registers using
the UPDATE clock. The data
stored in the UPDATE reigsters
can be used for the EXTEST
instruction.
SAMPLE/PRELOAD Instruction Mode
The SAMPLE/PRELOAD instruction mode allows you to take a snapshot of
device data without interrupting normal device operation. However, this
instruction is most often used to preload the test data into the update
registers prior to loading the EXTEST instruction.
capture, shift, and update phases of the SAMPLE/PRELOAD mode.
OUTJ
OUTJ
OEJ
OEJ
SDI
SDI
0
1
0
1
0
1
0
1
0
1
0
1
SHIFT
SHIFT
CLOCK
CLOCK
Registers
D
D
D
Capture
Registers
D
D
D
Capture
Q
Q
Q
Q
Q
Q
SDO
UPDATE
SDO
UPDATE
Registers
D
D
D
Update
D
D
D
Registers
Update
IEEE Std. 1149.1 BST Operation Control
Cyclone III Device Handbook, Volume 1
Q
Q
Q
Q
Q
Q
0
1
0
1
0
1
0
1
0
1
0
1
MODE
MODE
INJ
INJ
Figure 14–8
o
shows the
14–13