EP3C16F256I7N Altera, EP3C16F256I7N Datasheet - Page 125
EP3C16F256I7N
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EP3C16F256I7N
Description
Cyclone III
Manufacturer
Altera
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Altera Corporation-Preliminary
March 2007
that can feed GCLKs, or external clock outputs. These post-scale counters
range from 1 to 512 with a 50% duty cycle setting. The post-scale counters
range from 1 to 256 with any non-50% duty cycle setting. The sum of the
high/low count values chosen for a design selects the divide value for a
given counter.
The Quartus II software automatically chooses the appropriate scaling
factors according to the input frequency, multiplication, and division
values entered into the altpll megafunction.
Post-scale Counter Cascading
The Cyclone III PLLs supports post-scale counter cascading to create
counters larger than 512. This is implemented by feeding the output of
one C counter into the input of the next C counter as shown in
Figure
Figure 6–15. Counter Cascading
When cascading counters to implement a larger division of the high-
frequency VCO clock, the cascaded counters behave as one counter with
the product of the individual counter settings. For example, if C0 = 4 and
C1 = 2, then the cascaded value is C0 × C1 = 8.
1
6–15.
Post-scale counter cascading is automatically set by the Quartus
II software in the configuration file. It cannot be done using PLL
reconfiguration.
VCO Output
VCO Output
VCO Output
VCO Output
VCO Output
VCO Output
Cyclone III Device Handbook, Volume 1
C0
C1
C2
C3
C4
Hardware Features
6–25
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